As a conventional nonvolatile semiconductor memory device, a nonvolatile semiconductor memory device shown in FIGS. 10 to 12 is known (refer to Patent Document 1; Related Art 1). The nonvolatile semiconductor memory device relating to Related Art 1 comprises a first diffusion region 107, a selection gate 103, a second diffusion region (121 in FIG. 10), a floating gate 106, and a control gate 111 in a memory cell array (refer to FIGS. 10 and 11).
The first diffusion regions 107 extend in one direction on the surface of a substrate 101, and are provided in parallel and apart from each other. The first diffusion region 107 is used as a local bit line (LB). The selection gates (SG) 103 are disposed in regions between the neighboring first diffusion regions 107 on the substrate 101 intervened with an insulating film 102, and extend in the same direction as the first diffusion region 107. The second diffusion regions (121 in FIG. 10) are disposed on the surface of the substrate 101 outside the cell region and underneath the selection gates 103, and extend in a direction crossing the selection gates 103 outside the cell region on both sides. The second diffusion region (121 in FIG. 10) is used as a common source (CS). Floating gates 106 (FG) are storage nodes and disposed in regions between the first diffusion regions 107 and the selection gates 103 intervened with the insulating film 102, and they are arranged insularly, when viewed from a direction normal to the plane. The control gates 111 (CG) are provided over the floating gates 106 and the selection gates 103 intervened with an insulating film 108, disposed in parallel and apart from each other, and extend in a direction crossing the selection gates 103. The control gates 111 are used as word lines.
A first unit cell is constituted by one of the first diffusion regions 107 (LB) disposed on both sides of the selection gate 103, a floating gate 106, a control gate 111, and a selection gate 103, and a second unit cell is constituted by the other of the first diffusion regions 107, a floating gate 106, a control gate 111, and a selection gate 103. Each of the first diffusion regions 107 is shared by a plurality of neighboring unit cells. In this nonvolatile semiconductor memory device, an inversion layer 120 is created within the cell region on the surface of the substrate 101 below the selection gate 103 when a positive voltage is applied to the selection gate 103.
Voltages applied to the first diffusion region 107, the selection gate 103, the second diffusion region 121, the control gate 111, and the substrate 101 (a well 101a) are controlled by a drive circuit 122, a part of peripheral circuits of the semiconductor memory device.
The selection gates 103 are provided in a pair of selection gates SG0 and SG1 in an erase block 123 (refer to FIG. 12). Viewed perpendicularly to the plane, SG0 and SG1 are respectively formed into a comb shape, and the comb teeth of SG0 are disposed in the spaces between the comb teeth of SG1 at a predetermined interval. SG0 and SG1 are electrically connected to all unit cells in the erase block 123. The erase block 123 is constituted by a plurality of unit cells, and a block is constituted by those unit cells where electrons are simultaneously drawn out of the floating gates 106 when an erase operation is performed (the erase operation will be described later). A plurality of the erase blocks 123 exist in one semiconductor memory device.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2005-51227A